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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:32:50 04/27/2009 
-- Design Name: 
-- Module Name:    waitedTime - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity waitedTime is
    Port ( clockInput : in  STD_LOGIC;
           reStartTime : in  STD_LOGIC;
           busWaitedTime : out  STD_LOGIC_VECTOR (11 downto 0));
end waitedTime;

architecture Behavioral of waitedTime is
SIGNAL tempMyrioSeconde,tempMilliSeconde:INTEGER:=0;
begin
	waitedTimePr:PROCESS(clockInput)
	BEGIN 
		IF rising_edge(clockInput) THEN 
			IF reStartTime = '1' THEN 
				tempMilliSeconde <= 0;
				tempMyrioSeconde <= 1;
				busWaitedTime <= "000000000000";
			ELSE 
				IF tempMyrioSeconde = 10 THEN 
					tempMilliSeconde <= tempMilliSeconde+1;
					tempMyrioSeconde <= 1;
					busWaitedTime <= conv_std_logic_vector(tempMilliSeconde+1, 12);
				ELSE 
					tempMyrioSeconde <= tempMyrioSeconde + 1;
					busWaitedTime <= conv_std_logic_vector(tempMilliSeconde, 12);
				END IF;
			END IF;
			IF tempMilliSeconde > 4000 THEN -- Reset
				tempMilliSeconde <= 0;
			END IF;
		END IF;
	END PROCESS waitedTimePr;

end Behavioral;
